1. Field of the Invention
The present invention relates to a reconfigurable data processing device and method.
2. Description of the Related Art
As a reconfigurable processing device capable of reconfiguration, there are a reconfigurable processing device called a field programmable gate array (FPGA), and a reconfigurable processing device having a processor type processing unit.
The FPGA includes processing units including a lookup table (LUT), an AND-OR logical element, and a small-size memory, and interconnects the processing units through a switch. The FPGA further includes a memory for configuration separately from the other memory. Configurations of an arithmetic element include an LUT, a logical element or the like, and a processing unit having a small-size memory, are defined in accordance with data stored in the memory for configuration. The FPGA defines a selection state of the switch to regulate a connection state of the processing units, thus defining an operation of the reconfigurable processing device.
The reconfigurable processing device having the processing type processing unit includes an arithmetic logical unit (ALU) in place of the LUT and the AND-OR logical element. The reconfigurable processing device having the processor type processing unit further includes a control unit configured to time-sequentially control the ALU and the small-size memory, and a program memory for defining time-sequential control.
According to such a reconfigurable processing device, contents of the memory used for configuration or the program memory are updated to reconfigure the reconfigurable processing device.
There is also a device which includes a plurality of memories for configuration, prestores different pieces of configuration information in the memories, and selects one of the pieces of configuration information to update a configuration.
For example, Japanese Patent Application Laid-Open No. 2002-215382 describes a technology which provides configuration memories corresponding to a plurality of configurations in order to reduce an overhead of configuration time, and connects the memories in a ring shape. This technology enables reuse of configuration data.
Thus, there is a technology which executes configuration of the reconfigurable processing device during its operation to expand an application range or improve effectiveness thereof.
This is a so-called “dynamic reconfiguration technology”. In the dynamic reconfiguration, it is impossible to perform a desired operation during updating of the configuration, and accordingly, overall processing performance goes down.
In processing that has to be performed in real time, the updating of the configuration must be completed before data is supplied for processing. Therefore, time necessary for updating the configuration should be short.
Furthermore, in the dynamic configuration, data for configuration must be switched within a short time. Accordingly, a plurality of memory areas are required for configuration, and as a result, the bulk of hardware increases.